я думаю не в тактовой дело, а в том, что TDM data is received most significant bit (MSB) first, on the second rising edge of the SCLK occurringafter a an FS rising edge. All data is valid on the rising edge of SCLK.

Кроме того, Each time slot is 32 bits wide, with the valid data sample left ‘justified within the time slot.Valid data lengths are 16, 18, 20, or 24. Надо 2*16Х8